Register organization is the arrangement of the registers in the processor. The processor designers decide the organization of the registers in a processor. Different processors may have different register organization. Depending on the roles played by the registers they can be categorized into two types, user-visible register and control and status register. Before learning register …
Cache Coherence assures the data consistency among the various memory blocks in the system, i.e. local cache memory of each processor and the common memory shared by the processors. It confirms that each copy of a data block among the caches of the processors has a consistent value. In this section, we will discuss the …
Direct Memory Access (DMA) transfers the block of data between the memory and peripheral devices of the system, without the participation of the processor. The unit that controls the activity of accessing memory directly is called a DMA controller. The processor relinquishes the system bus for a few clock cycles. So, the DMA controller can …
RISC is an abbreviation of Reduced Instruction Set Computer. RISC processor has ‘instruction sets’ that are simple and have simple ‘addressing modes’. A RISC style instruction engages “one word” in memory. Execution of the RISC instructions are faster and take one clock cycle per instruction. Although the forerunners of RISC computers were seen in 1960. …
The Hardwired and Microprogrammed control unit generates the control signals to fetch and execute instructions. The fundamental difference between hardwired and microprogrammed control unit is that hardwired is a circuitry approach whereas, the microprogram control unit is implemented by programming. The hardwired control unit is designed for the RISC style instruction set. On the other …
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CISC is an abbreviation for Complex Instruction Set Computer. CISC processors were evolved in the 1970s before the evolution of RISC (Reduced Instruction Set Computers) processors. During this period the computer memory uses to be ‘small’ and ‘very expensive’. CISC processors were helpful in simplifying the code and making it shorter in order to reduce …
Addressing modes specifies the way, the effective address of an operand is represented in the instruction. Some addressing mode efficiently allows referring to a large range of area like a linear array of addresses and list of addresses. Addressing mode describes a flexible and efficient way to define complex effective address. Generally, the programs are …
Instructions in a program have proper instruction format and sequencing which decides the flow of the program execution. There are several types of instructions in a computer program like: instruction performing arithmetic or the logic operation on the numbers instruction that branches to other instruction in the program the instruction that checks the particular condition …
Vector processing performs the arithmetic operation on the large array of integers or floating-point number. Vector processing operates on all the elements of the array in parallel providing each pass is independent of the other. Vector processing avoids the overhead of the loop control mechanism that occurs in general-purpose computers. In this section, we will …
Pipelining organizes the execution of the multiple instructions simultaneously. Pipelining improves the throughput of the system. In pipelining the instruction is divided into the subtasks. Each subtask performs the dedicated task. The instruction is divided into 5 subtasks: instruction fetch, instruction decode, operand fetch, instruction execution and operand store. The instruction fetch subtask will only …