Control Signals in Computer Architecture

Control signals regulate the operations and coordination of all processor components while executing the instructions. It is the control unit of the CPU, which is responsible for generating control signals. If we divide the instruction cycle into two phases, it would be the fetch phase and the execution phase.

Even the processor’s hardware is divided into two sections. The section that deals with the fetch phase also generates control signals. We refer to this section or unit as the Control Unit. The other section deals with the execution phase read the data operands of instruction, performs the required computation, and stores the result. We often refer to this unit as ALU.

Thus, the control unit generates control signals so that the processing of instructions takes place in the correct sequence and at the right time.

How are Control Signals Generated?

There are two approaches to design a control unit for generating the control signals.

1. Hardwired Control
2. Microprogrammed Control

Hardwired Control

To execute a particular instruction, a system needs to execute a sequence of steps such as:

1. Instruction fetch
2. Instruction decoding
3. Operand fetch
4. Instruction execution
5. Operand store

Each of these steps requires one clock cycle. Particularly to track the progress in the execution, the system employs a step counter. The status of the step counter indicates currently which execution step is in process. For each execution step, we require control signals.

Consequently, the system has to perform several actions for a single execution step. The actions depend on the type of instruction in execution like:

• For a branch instruction, the action depends on the test applied.
• Even the interrupt signal can influence the action.

So, the generation of the control signal totally depends on the following:

1. Status of step counter.
2. Content of instruction register.
3. The output of the comparison operation.
4. External signals like interrupts.

Hardwired Control Diagram

1. Initially, the instruction decoder interprets the instruction in IR and obtains its addressing modes.
2. After decoding the instruction, the instruction decoder activates the corresponding INSi.
3. Parallelly the step counter activates its output from T1 to T5 to trace which of the five steps (instruction fetch, instruction decoding, operand fetch, instruction execution, and operand store) between fetching and execution is in process.
4. Based on all the inputs, the control unit generates the control signals.
5. The action sequences represented by signals INS1 to INSm determine the settings of the control signals.

However, the hardwired unit preferably generates the signals for RISC-style instructions.

Besides using the hardwired control to generate a control signal, designers used one popular alternative in the past. We will discuss it in the next section, i.e. microprogrammed control.

Microprogrammed Control

The hardwired control uses logic circuitry to generate the control signals. However, the microprogrammed control uses software to generate control signals. The control signals’ settings in the microprogrammed unit depend on a special program (control program) stored in a special memory.

We refer to the control program as a microprogram so that it can be easily distinguished from the other programs that the processor executes. The memory holding the microprogram is microprogram memory, or we refer to it as the control store.

While executing an instruction, we require multiple control signals for each step. Each control signal is represented by a bit in n bit-word. We refer to this word as a control word or a microinstruction. In a control word, each bit indicates the setting of the corresponding control signal required for a particular step in the execution flow.

So, to execute an instruction, for each step (instruction fetch, instruction decoding, operand fetch, instruction execution, and operand store), one control word/microinstruction is stored in the control store. The sequence of microinstructions required to execute an instruction constitutes the microroutine.

The first two microinstructions that specify the action of fetch and decode are the same for all instructions. The micro routine specific to any instruction starts from the third step, i.e. from operand fetch.

Microprogrammed Control Diagram

1. The microinstruction address generator decodes the instruction in IR and obtains the starting address of the micro routine.
2. Meanwhile, this micro routine holds the sequence of microinstructions required to implement the instruction in IR.
3. The microinstruction generator loads the starting address of the micro routine to µPC.
4. In the following clock cycle, the address in µPC will be used to read the microinstruction as the execution proceeds, and the microinstruction generator increments µPC to read the execution microinstruction.

As the execution of the instruction ends, the microinstruction address generator returns back to the first microinstruction, which causes new instruction to be fetched in IR. However, we use microprogrammed control to generate control signals for CISC-style instructions.

The microinstruction is much more executed like a machine instruction. Its function is to generate control signals required during each execution of a step while implementing the instruction.